The present invention relates generally to the field of microelectronic device fabrication, and more particularly to the deposition of metal onto a semiconductor wafer, and specifically to the electroplating of copper into a cavity formed on a semiconductor wafer.
Electroplating of metals is a well known technology that has recently become more widely used in the manufacture of microelectronic devices such as integrated circuits formed on semiconductor wafers. Electroplating provides a higher deposition rate than thermal deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or sputtering, and will do so at a significantly lower temperature. As a result, electroplating is a relatively low cost process for material deposition.
Electroplating involves the immersion of a surface to be plated into a solution containing ions of the metal to be deposited. An electrical charge is applied between the solution and the surface, and the metal ions are attracted to the surface where they are reduced to a metal which then plates out onto the surface. For the deposition of copper on a semiconductor wafer surface, the solution may contain, among others, copper sulfate (CuSO4), sulfuric acid (H2SO4), other additives and water. The cupper sulfate will break down in this acid solution to form constituent ions. The semiconductor wafer surface is prepared by the deposition of an adhesion/barrier layer and a seed layer. The adhesion/barrier layer may be tantalum, tantalum nitride or other refractory metallic film. The function of the seed layer is to provide a material on which a subsequently deposited material will readily form. The seed layer may be a thin layer (approximately 100 nm) of copper or other suitable material known in the art and applied by PVD or other process known in the art. The wafer and prepared surface are brought in contact with a bath containing the solution, an electrical charge is applied and copper is deposited.
FIG. 1 illustrates a prior art semiconductor device 10 having a layer of copper 12 deposited on a silicon wafer 14. The device 10 includes a barrier layer 16 and a seed layer 18 deposited on the wafer 14 prior to the electro-deposition of the copper layer 12. Prior to the deposition of the various layers 16, 18, 12, there was formed a cavity 20, such as a trench, via or dual damascene structure, in the top surface of the wafer 14. One may appreciate that the cavity 20 may be formed directly into the silicon wafer 14 or into one or more layers of dielectric or other materials formed over the silicon, depending upon the requirements of the particular application. The layer of copper 12 may be approximately 0.5-2.5 microns in thickness, while the depth of the cavity 20 may vary from about 0.1 micron to about 1.5 micron. The top portion of the deposited copper is removed by a chemical mechanical polishing (CMP) process or other planarization method to form the final device 22 as illustrated in FIG. 2. The extra depth of copper is deposited to ensure a full fill in the cavity 20 and to provide sufficient material to ensure that a planar surface can be obtained via the planarization process.
One may appreciate that as the depth/width ratio of cavity 20 increases, it becomes increasingly more difficult to ensure that the fill metal is deposited throughout the entire volume of the cavity 20. Certain additives are commonly used with the electrolyte solution to facilitate a complete bottom-up fill of cavity 20 and/or to provide desired mechanical properties to the as-deposited metal. While the cost of a plating process may be less than alternative thermal deposition processes, the cost of the additives used in the plating solution can be significant.
With the demand for microelectronics products being directly responsive to their price in the marketplace, there is continuing pressure to reduce the cost of manufacturing of these devices. Accordingly, a less costly electroplating process is needed.
A microelectronic device is described at a stage of fabrication as including: a substrate having a surface; a layer of a metal plated onto the substrate surface; and a first region of the layer of metal having a first chemical composition and a second region of the layer of metal plated over the first region and having a second chemical composition different from the first chemical composition. The layer of metal may include a metal and an additive, and wherein the concentration of the additive varies across a depth of the layer of metal. The metal may be copper and the additive may be at least one of the group of a carrier, a leveler and a surfactant. The device may further include: the substrate having a surface with a generally planar field area and a cavity formed therein; and the first region extending from the substrate surface to a level at least filling the cavity.
A process for fabricating a microelectronic device is described herein as including: depositing a layer of material on a surface of a semiconductor wafer by contacting the surface with a plating solution; and changing the chemical composition of the plating solution during the step of depositing so that the deposited layer of material comprises a plurality of regions each having a different chemical composition. The process may further include: forming a cavity on the surface of the semiconductor wafer prior to the step of depositing; and changing the chemical composition of the plating solution after the deposited layer of material has been deposited to a predetermined thickness in the cavity.
A process for fabricating a microelectronic device, the process comprising: depositing a first region of a layer of material on a surface of a semiconductor wafer in a first plating cell by contacting the surface of the semiconductor wafer with a first plating solution having a first chemical composition; and depositing a second region of the layer of material on the first region in a second plating cell by contacting a surface of the first region with a second plating solution having a second chemical composition different from the first chemical composition.
A device for depositing a layer of metal having a plurality of regions with distinct chemical compositions is described as including: a first solution tank and a second solution tank for containing respective first and second plating solutions having distinct chemical compositions; and a bath connected to the first solution tank and to the second solution tank for receiving consecutive volumes of the first and second plating solutions.
A device for depositing a layer of metal having a plurality of regions with distinct chemical compositions is further described as including: a first bath for containing a first plating solution having a first chemical composition; a second bath for containing a second plating solution having a second chemical composition different than the first chemical composition; and a handling tool for moving a wafer from the first bath to the second bath.